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INTEGRATED CIRCUITS
DATA SHEET
74LVC32245A; 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Product specification File under Integrated Circuits, IC24 1999 Sep 01
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
FEATURES * 5 V tolerant inputs/outputs for interfacing with 5 V logic * Wide supply voltage range of 1.2 to 3.6 V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTETM flow-trough standard pin-out architecture * Low inductance multiple power and ground pins for minimum noise and ground bounce * Direct interface with TTL levels * Bus hold on data inputs (74LVCH32245A only) * Typical output ground bounce voltage: VOLP < 0.8 V at VCC = 3.3 V; Tamb = 25 C * Typical output VOH undershoot voltage: VOHV > 2 V at VCC = 3.3 V; Tamb = 25 C * Power-off disabled outputs, permitting live insertion * Plastic fine-pitch ball grid array package. DESCRIPTION
74LVC32245A; 74LVCH32245A
The 74LVC(H)32245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. The 74LVC(H)32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74LVC(H)32245A features two output enable (nOE) inputs for easy cascading and two send or receive (nDIR) inputs for direction control. nOE controls the outputs so that the buses are effectively isolated. To ensure the high-impedance state during power-up or power-down, input nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74LVCH32245A bus hold data inputs eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level (see Fig.2).
QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CI CI/O CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of the outputs. PARAMETER propagation delay nAn to nBn; nBn to nAn input capacitance input/output capacitance power dissipation capacitance per buffer VI = GND to VCC; note 1 CONDITIONS CL = 50 pF; VCC = 3.3 V 3.0 5.0 10 30 TYPICAL ns pF pF pF UNIT
1999 Sep 01
2
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
FUNCTION TABLE See note 1. INPUT nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGES TYPE NUMBER TEMPERATURE RANGE 74LVC32245AEC 74LVCH32245AEC PINNING SYMBOL nDIR nOE nAn nBn GND VCC direction control output enable input (active LOW) data inputs/outputs data inputs/outputs ground (0 V) DC supply voltage DESCRIPTION -40 to +85 C PINS 96 96 PACKAGE LFBGA96 LFBGA96 nDIR L H X nAn A=B inputs Z
74LVC32245A; 74LVCH32245A
OUTPUT nBn inputs B=A Z
MATERIAL plastic plastic
CODE SOT536-1 SOT536-1
1999 Sep 01
3
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
74LVC32245A; 74LVCH32245A
handbook, full pagewidth
MNA475
6 5 4 3 2 1
1A1 1A0
1A3 1A2
1A5 1A4
1A7 1A6
2A1 2A0
2A3 2A2
2A5 2A4
2A6 2A7
3A1 3A0
3A3 3A2
3A5 3A4
3A7 3A6
4A1 4A0
4A3 4A2
4A5 4A4
4A6 4A7
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 1B0 1B1 A 1B2 1B3 B 1B4 1B5 C 1B6 1B7 D 2B0 2B1 E 2B2 2B4 2B7 3B0 3B1 J 3B2 3B3 K 3B4 3B5 L 3B6 3B7 M 4B0 4B1 N 4B2 4B3 P 4B4 4B5 R 4B7 4B6 T
2B3 2B51 2B6 F G H
Fig.1 Pin configuration.
handbook, halfpage
VCC
data input
to internal circuit
MNA473
Fig.2 Bus hold circuit.
1999 Sep 01
4
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ook, full pagewidth
1999 Sep 01
A3 1DIR 1OE A5 1A0 1B0 A6 1A1 1B1 B5 1A2 1B2 B6 1A3 1B3 C5 1A4 1B4 C6 1A5 1B5 D5 1A6 1B6 D6 1A7 1B7 D1 D2 H5 2A7 2B7 H2 C1 H6 2A6 2B6 H1 C2 G6 2A5 2B5 G1 B1 G5 2A4 2B4 G2 B2 F6 2A3 2B3 F1 A1 F5 2A2 2B2 F2 A2 E6 2A1 2B1 E1 H3 A4 E5 2A0 2B0 E2 2DIR 2OE H4
Philips Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
J3
3DIR 3OE
T3 J4 N5 3B0 J2 N6 3B1 J1 P5 3B2 K2 P6 3B3 K1 R5 3B4 L2 R6 3B5 L1 T6 3B6 M2 T5 3B7 M1
4DIR 4OE 4A0 4B0 4A1 4B1 4A2 4B2 4A3 4B3 4A4 4B4 4A5 4B5 4A6 4B6 4A7 4B7
MNA476
T4
J5
3A0
N2
J6
3A1
N1
K5
3A2
P2
K6
3A3
P1
L5
3A4
5
R2
L6
3A5
R1
M5
3A6
T1
M6
3A7
T2
74LVC32245A; 74LVCH32245A
Product specification
Fig.3 Logic symbol.
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
RECOMMENDED OPERATING CONDITIONS
74LVC32245A; 74LVCH32245A
LIMITS SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER DC supply voltage DC input voltage DC output voltage operating ambient temperature input rise and fall times ratio output HIGH or LOW state 3-state see DC and AC characteristics per device VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS MIN. for max. speed performance for low-voltage applications 2.7 1.2 0 0 0 -40 0 0 MAX. 3.6 3.6 5.5 VCC 5.5 +85 20 10 V V V V V C ns/V UNIT
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 70 C the value of PD derates linearly with 1.8 mW/K. PARAMETER DC supply voltage DC input voltage DC input diode current DC output diode current DC output voltage DC output source or sink current DC VCC or GND current storage temperature power dissipation per package temperature range: -40 to +85 C; note 2 note 1 VI < 0 VO > VCC or VO < 0; note 1 output 3-state; note 1 VO = 0 to VCC CONDITIONS MIN. -0.5 -0.5 - - -0.5 - - -65 - MAX. +6.5 +6.5 -50 50 VCC + 0.5 +6.5 50 100 +150 1000 UNIT V V mA mA V V mA mA C mW
output HIGH or LOW state; note 1 -0.5
1999 Sep 01
6
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
DC CHARACTERISTICS Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -12 mA IO = -100 A IO = -18 mA IO = -24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 12 mA IO = 100 A IO = 24 mA II IOZ Ioff ICC ICC IBHL IBHH IBHLO IBHHO Notes 1. All typical values are at VCC = 3.3 V and Tamb = 25 C. input leakage current 3-state output OFF-state current VI = 5.5 V or GND; note 2 VI = VIH or VIL; VO = 5.5 V or GND VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 2.7 3.0 3.0 3.6 3.6 0.0 3.6 - - - - - - - 2.7 3.0 3.0 3.0 VCC (V) 1.2 1.2
74LVC32245A; 74LVCH32245A
Tamb (C) -40 to +85 MIN. VCC - TYP.(1) MAX. - - - - - - GND 0.8 - - - - 0.40 0.20 0.55 5 5 10 40 500 - - - - A A A A A A A A A V V V V UNIT
2.7 to 3.6 2.0 2.7 to 3.6 -
VCC - 0.5 - VCC - 0.2 VCC VCC - 0.6 - VCC - 0.8 - - - - 0.1 0.1 0.1 0.1 5 - - - -
power off leakage supply current VI or VO = 5.5 V quiescent supply current additional quiescent supply current per input pin
2.7 to 3.6 - 3.0 3.0 3.6 3.6 75 -75 500 -500
bus hold LOW sustaining current VI = 0.8 V; notes 3, 4 and 5 bus hold HIGH sustaining current VI = 2.0 V; notes 3, 4 and 5 bus hold LOW overdrive current bus hold HIGH overdrive current notes 3, 4 and 6 notes 3, 4 and 6
2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal. 3. Valid for data inputs of bus hold parts only (LVCH32xxx-A). 4. For data inputs only. Control inputs do not have a bus hold circuit. 5. The specified sustaining current at the data input holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input level.
1999 Sep 01
7
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
AC CHARACTERISTICS Ground = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ PARAMETER WAVEFORMS propagation delay nAn to nBn; nBn to nAn 3-state output enable time nOE to nAn; nOE to nBn 3-state output disable time nOE to nAn; nOE to nBn see Figs 4 and 6 see Figs 5 and 6 see Figs 5 and 6 VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6
74LVC32245A; 74LVCH32245A
Tamb = -40 to +85 C MIN. 1.5 1.5 1.5 1.5 1.5 1.5 TYP.(1) - 3.0 - 4.0 - 4.0 MAX. 5.5 4.5 7.1 6.1 6.6 5.6
UNIT ns ns ns
Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. AC WAVEFORMS
handbook, halfpage VI
nAn, nBn INPUT GND t PHL VOH nBn, nAn OUTPUT VOL
VM
t PLH
VM
MNA477
VM = 1.5 V at VCC 2.7 V or VM = 0.5 x VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times.
1999 Sep 01
8
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
74LVC32245A; 74LVCH32245A
handbook, full pagewidth
VI nOE INPUT GND t PLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL t PHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX t PZH t PZL VM
outputs disabled
outputs enabled
MNA478
VM = 1.5 V at VCC 2.7 V or VM = 0.5 x VCC at VCC < 2.7 V; VX = VOL + 0.3 V at VCC 2.7 V or VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH - 0.3 V at VCC 2.7 V or VY = VOH - 0.1 V at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 3-state enable and disable times.
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 VO RL 500
2 x VCC open GND
MNA479
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 open 2 x VCC GND VCC < 2.7 V VCC VI
2.7 to 3.6 V 2.7 V
Definitions for test circuit: RL = load resistor. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
1999 Sep 01
9
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
PACKAGE OUTLINE
74LVC32245A; 74LVCH32245A
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
SOT536-1
D ball A1 index area
A2 E A1 detail X
A
b e T R P N M L K J H G F E D C B A 123456
w M
A vA y
ZD ZE
e
X
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 v 0.2 w 0.15 y 0.1 ZD 0.93 0.58 ZE 0.93 0.58 0 5 scale 10 mm
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 98-11-25 99-06-03
1999 Sep 01
10
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74LVC32245A; 74LVCH32245A
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Sep 01
11
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
74LVC32245A; 74LVCH32245A
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable REFLOW(1)
1999 Sep 01
12
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
NOTES
74LVC32245A; 74LVCH32245A
1999 Sep 01
13
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
NOTES
74LVC32245A; 74LVCH32245A
1999 Sep 01
14
Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
NOTES
74LVC32245A; 74LVCH32245A
1999 Sep 01
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/01/pp16
Date of release: 1999
Sep 01
Document order number:
9397 750 06259

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